Minimizing plating stub reflections in a chip package using capacitance

ABSTRACT

The present invention is directed to shifting the resonant frequency in a high-frequency chip package away from an operational frequency by connecting a capacitance between an open-ended plating stub and ground. One embodiment provides a method including capacitively coupling a plating stub to ground so that the resonant frequency caused by the plating stub in a semiconductor package is shifted away from an operational frequency.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional of U.S. patent application Ser. No.12/237,444 filed on Sep. 25, 2008, which application is incorporated byreference herein.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to chip packages, and more specifically toaddressing the problem of resonance due to plating stubs inhigh-frequency chip packages.

2. Background of the Related Art

An integrated circuit (IC), also commonly referred to as a “microchip”or “chip,” is an electronic circuit comprising miniaturizedsemiconductor devices formed in a semiconductor substrate. Many copiesof a chip may be formed on a large semiconductor wafer and then cut intoindividual chips, which may be interchangeably referred to in the art asa “die chips” or “dies”. However, semiconductor materials such assilicon are typically brittle, and chips made this way are fragile.Therefore, an individual die chip is commonly packaged on a carrier,referred to as a “chip package” or simply “package.” The housing of thechip package protects the chip and the package provides an electricaland mechanical interface between the chip and a printed circuit board(PCB) such as a computer motherboard.

Electrical connections between a die chip and the package substrate maybe made by wirebonding. Wirebonding is a process known in the art bywhich a very fine wire is connected from a bond pad on the chip tocorresponding signal pathways (“traces”) on the package substrate. Bondwires are typically formed of a highly conductive material, such asplatinum or other precious metal. A package in which a die chip isconnected to the substrate by wirebonding may be referred to as a“wirebond package.” The traces on the substrate extend from the locationof bonding with the wirebond to signal interconnects elsewhere on thesubstrate.

The signal interconnects on one layer of the substrate may beelectrically connected to signal interconnects on another layer of thesubstrate using through-connections known as “vias.” Thus, for example,the signal connects on the face to which the chip is mounted may beconnected to corresponding pins of a pin grid array (PGA) or tocorresponding balls of a ball grid array (BGA) on the opposing face ofthe substrate. The PGA or BGA may then be placed in contact with acorresponding pattern of electrical contacts on the PCB to which thechip package is subsequently secured.

Signal traces are typically formed of commonly available materials, suchas copper, that are relatively affordable and have sufficient electricalconductivity. Materials having improved electrical conductivity,including precious metals such as platinum and gold, are thenselectively applied to the substrate at locations where the expense ofsuch materials is warranted. For example, to facilitate wire bonding,platinum may be applied at locations along the signal traces where wirebonds are formed. Gold is often applied to signal interconnects. Thesematerials are usually applied by electroplating. However, mostelectroplating processes result in open plating stubs extending from thesignal interconnects. The electroplating voltage is applied at or nearthe periphery of the package substrate, which results in the platingstubs extending to or near the periphery of the substrate. Plating stubsmay hinder signal performance of the package if left intact. Signalperformance is greatly impacted by reflections from the open stubs atthe high operational frequencies of modern chips. A quarter-wave lengthresonance is particularly detrimental in high speed data transmissions.

BRIEF SUMMARY OF THE INVENTION

One embodiment of the present invention provides a method, comprisingcapacitively coupling a plating stub to ground so that the resonantfrequency caused by the plating stub in a semiconductor package isshifted away from an operational frequency.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

FIG. 1 is a schematic side view of a surface-mount, semiconductor chippackage configured for assembly to a surface of a printed circuit board.

FIG. 2 is a plan view of the package substrate of FIG. 1, including anenlarged view of a portion of the substrate showing the open-endedplating stubs.

FIG. 3 is a schematic plan view of the package substrate of FIG. 1wherein capacitance is connected between one of the plating stubs andground to shift the quarter-wave-length resonance to a lower frequencyband.

FIG. 4 is a graph illustrating the resonant frequency shift by virtue ofconnecting the capacitance between a plating stub and ground.

FIG. 5 is a side view of an embodiment of a package substrateincorporating a discrete capacitor connected between the plating stuband ground.

FIG. 6 is a side view of an embodiment of a package substrateincorporating an embedded capacitance for connecting between the platingstub and ground.

FIG. 7 is a side view of another embodiment of a package substrateincorporating an alternative embedded capacitance for connecting betweenthe plating stub and ground.

DETAILED DESCRIPTION OF THE INVENTION

The present invention may be embodied as a method of shifting theresonant frequency in a high-frequency chip package by capacitivelycoupling an open-ended plating stub to ground. The plating stub may becapacitively coupled to ground using a discrete capacitor or a capacitorstructure formed within a multi-layered package substrate. Likewise, theinvention may also be embodied as a multi-layered package substrate in ahigh-frequency chip package, wherein an open-ended plating stub iscapacitively coupled to ground. Capacitively coupling a plating stub toground according to the invention provides an effective way to minimizeplating stub reflections, and is more economical than other approachesto mitigating the effects of plating stubs. The invention may be appliedin its various embodiments to a multitude of chip package configurationsknown in the art. Principles of the invention discussed in relation tothe illustrated embodiments, therefore, may also be applied toconfigurations of a chip package other than the illustrated chippackage.

A first exemplary embodiment of the present invention provides amulti-layer substrate for interfacing a chip with a printed circuitboard. A first outer layer provides a chip mounting location. A signalinterconnect is spaced from the chip mounting location. A signal traceextends from near the chip mounting location to the signal interconnect,and a plating stub extends from the signal interconnect. A capacitorcouples the plating stub to a ground layer.

A second exemplary embodiment of the invention provides a chip package.A substrate included with the chip package has a first face and anopposing second face. A chip is secured to the first face. A signaltrace electrically connects the chip to a signal interconnect along thefirst face of the substrate. A plating stub extends outwardly from thesignal interconnect, and a capacitor connects the plating stub toground. An electrical contact disposed along the first or second face isconfigured for mating with a corresponding electrical contact on aprinted circuit board.

A third exemplary embodiment of the invention provides a method,comprising shifting the resonant frequency caused by a plating stub in asemiconductor package away from an operational frequency by capacitivelycoupling the plating stub to ground.

FIG. 1 is a schematic side view of a surface-mount, semiconductor chippackage 20 configured for assembly to a surface of a printed circuitboard (PCB) 10. The package substrate 40 only shows two layers forsimplicity of illustration, but such a substrate usually has multiplelayers. The package 20 includes a chip 22 mounted on a first face 23 ofa package substrate 40. Although not required, the chip 22 may beenclosed in a protective housing 26, such as molded plasticencapsulating the chip 22. The chip 22 is electrically connected to aball grid array (BGA) disposed on a second face 25 opposite the firstface 23. In the orientation shown, the first face 23 may be referred toas the top face and the second face 25 may be referred to as the bottomface. The array of balls 30 are aligned for contact with a correspondingpattern of electrical contacts or pads 12 on the PCB 10. The balls 30may be heated to melting or softening while in contact with theelectrical pads 12 on the PCB 10, and then cooled to secure the BGA. Asan alternative, pins or other electrical contacts may be provided on thesubstrate 40 in lieu of a ball grid array, with an appropriate choice ofelectrical contacts on the PCB 10 for mating with the pins or otherelectrical contacts on the substrate 40.

FIG. 2 is a plan view of the package substrate 40 without the chip 22,housing 26 or bond wires 28. The figure includes an enlarged view of aportion 41 of the substrate 40. The substrate 40 provides a centrallylocated chip mounting location 42 for receiving the chip 22 (see FIG.1). A plurality of discrete electrical pathways, embodied here as signaltraces 44, are formed on the substrate 40. The signal traces 44 may beformed according to known techniques in the art of circuit boardmanufacturing. The signal traces 44 may be formed, for example, by asubtractive process, in which a sheet of copper or other conductivematerial laminated to the substrate 40 is etched away to leave thedesired pattern of traces. Less commonly, the signal traces 44 may beformed by an additive process, in which copper is plated onto thesubstrate 40 in the desired pattern such that no etching is required. Aplurality of signal interconnects 46 (alternatively referred to aselectrode pads) are shown position across the top face 23 of thesubstrate 40. The signal interconnects 46 are concentric with vias,which are through-holes extending through the substrate 40. Each signaltrace 44 extends radially outwardly from the chip mounting location 42to a corresponding one of the signal interconnects 46.

Features of the substrate 40 may be electroplated, such as the signalinterconnects 46, the vias concentric with the signal interconnects 46,and portions of the signal traces 44 where bond wires are to beattached. As best shown in the enlarged portion 41, a plurality ofopen-ended plating stubs 48 extend outwardly from many of the signalinterconnects 46 in a direction away from the chip mounting location 42to a periphery 49 of the substrate 40. The plating stubs for othersignal interconnects are routed on the opposite side of the substrate 40from BGA pads to the periphery 49. The signal traces 44 and the platingstubs 48 extend radially outwardly from the centrally located chipmounting location 42, although it is not necessary for the signal traces44 or plating stubs 48 to be straight or lie exactly on radii extendingfrom a common center.

The plating stubs 48 are open ended by virtue of extending past therespective signal interconnects 46 without connecting to another deviceor conductive pathway. Typically, the open plating stubs 48 extend allthe way from one of the signal interconnects 46 to or near the periphery49 of the substrate 40, because to perform gold plating for electrodepads on the substrate 40, the electrode pads must be rendered conductivefrom the outer edge of the interposer. However, the invention may beembodied even on a substrate wherein the plating stubs do not extendfully to a periphery 49. For example, any present or future-developedelectroplating process that results in an open plating stub extendingradially outward from a signal interconnect may benefit from anembodiment of the invention, regardless of whether the plating stubextends completely to the periphery of a package substrate.

FIG. 3 is a schematic plan view of the package substrate 40 wherein acapacitor 50 is connected between a plating stub 48A and ground to shiftthe quarter-wave-length resonance caused by the presence of the platingstub 48A to a lower frequency band. The capacitor 50 may take the formof a discrete capacitor or an embedded capacitor formed in the substrate40, examples of which are discussed in relation to FIGS. 5, 6, and 7. Aparticular signal trace 44A is electrically coupled to the chip 22, e.g.using a bond wire, and extends radially outwardly from the chip 22 to aparticular signal interconnect 46A. The open-ended plating stub 48Aextends outwardly from the signal interconnect 46A to the periphery 49of the substrate 40. The capacitor 50 is connected between the platingstub 48A and ground, in this case by virtue of connection to a “ground”signal interconnect 46B. The ground signal interconnect 46B is inelectrical communication with a ground layer in the multi-layersubstrate 40.

FIG. 4 is a graph illustrating the resonant frequency shift caused bycapacitively coupling of a plating stub to ground. Curve 1 illustratesthe signal performance for signals communicated along the signal trace44A in FIG. 3, assuming the plating stub 48A has a stub length of 7 mm.The local maxima (peak) of Curve 1 indicates a resonant frequencyoccurring at about 7 GHz, which is the operational frequency of signalscommunicated along the signal trace 44A. The 7 GHz resonant frequencycaused by the presence of the plating stub 48A imposes substantialsignal interference, and is detrimental to high-speed signaltransmission along the signal trace 44A. Curve 2 illustrates the signalperformance for signals communicated along the signal trace 44A in FIG.3, after a 50 picofarad (pF) capacitance has been added between theplating stub and ground. The resonant frequency is shifted to less than1 GHz as a result of the added capacitance, which avoids the operationalfrequency and greatly reduces or eliminates the interference that wouldotherwise be caused by an open plating stub. In this example, there isan improvement of approximately 15 dB by adding the 50 pF capacitance.

A myriad of possible layering configurations in a package substrate arepossible. Additionally, a variety of capacitor types may be selectedaccording to different embodiments of the invention. Accordingly, asubstrate incorporating capacitance between a plating stub and ground,as schematically shown in FIG. 3, may be embodied in many differentways, examples of which are shown in FIGS. 5-7. In the examples thatfollow, FIG. 5 shows an embodiment of a substrate using a discretecapacitor, while FIGS. 6 and 7 show alternative embodiments of asubstrate using an embedded capacitor.

FIG. 5 is a cross-sectional side view of an embodiment of a packagesubstrate 140 incorporating a discrete capacitor 150 for connecting theplating stub 48A to ground. The capacitor 150 includes a first lead 154connected to the plating stub 48A and a second lead 152 connected to theground signal interconnect 46B according to an embodiment of theinvention. The ground signal interconnect 46B on the top face 23 of thesubstrate 140 is connected through the substrate 140 by a via 70 to aground signal interconnect 46C on the opposing, bottom face 25 of thesubstrate 140. A conductive ball 30 from the ball grid array is incontact with the ground signal interconnect 46C. When the substrate 140is connected to a PCB, the ground signal interconnect 46C may be placedin contact with a ground terminal on the PCB, so that the capacitor 150is connected between the plating stub 48A and ground.

The use of a discrete capacitor, such as in FIG. 5, can be a relativelylow cost solution to providing capacitance for shifting the resonantfrequency away from the operational frequency according to an aspect ofthe invention. However, an alternative to a discrete capacitor is an“embedded capacitor,” which may be interchangeably referred to as a“buried capacitor.” An embedded capacitor avoids the particular noiseproblems that can be caused by the presence of capacitor leads in adiscrete capacitor. A buried capacitor in the context of a packagesubstrate typically includes a layer of dielectric sandwiched betweentwo metal layers, formed as part of a multi-layer package substrate. Onemetal layer may be provided in a power or ground plane and the othermetal layer may be provided in a ground plane.

FIG. 6 is a cross-sectional side view of an embodiment of amulti-layered package substrate 240 incorporating an embedded capacitor250 for connecting the plating stub 48A to ground. Each layer of thesubstrate 240 lies in a respective plane 260, indicated by dashed lines.The substrate 240 may have any number of multiple layers, and acomprehensive discussion of every layer is not required here. Thesubstrate 240 includes a dielectric layer (“DIEL”) sandwiched between aground layer (“GND”) and a power layer (“PWR”). The GND and PWR layersare above the bottom face 225 at the bottom of the substrate 240. Theplating stub 48A extends along the bottom face 225 of the substrate 240from a first interconnect (not shown) to the via 70. The via 70electrically connects the plating stub 48A to a capacitor plate 272formed in the PWR layer. The capacitor plate 272 is an isolatedconductor, separated from other elements in the PWR layer by gaps 273.The capacitor plate 272 is isolated from other elements in the PWRlayer. A portion of the GND layer opposite the first capacitor plate 272serves as a second capacitor plate 274, which is separated from thefirst capacitor plate 272 by the DIEL layer. Thus, the embeddedcapacitor 250 includes the first and second capacitor plates 272, 274separated by the DIEL layer. By connecting the plating stub 48A toground using the capacitor 250, signal reflections in the plating stub48A are altered. Specifically, the presence of the embedded capacitor250 alters the behavior of electrical activity in the plating stub 48Aby shifting the resonant frequency as exemplified in the graph of FIG.4.

FIG. 7 is a cross-sectional side view of the multi-layered packagesubstrate 340 incorporating an alternative embedded capacitor 350 forconnecting the plating stub 48A to ground. The number of layers 360 ofthe substrate 340 in this embodiment may be different than the number oflayers 260 in the embodiment of FIG. 6. The substrate 340 includes aground layer (“GND”) and a signal layer (“SIG”). The GND and SIG layersare inwardly located from the outermost plane that contains an outersignal layer 325 at the bottom of the substrate 340. The plating stub48A extends along the outer signal layer 325 of the substrate 340 to thevia 70. The via 70 electrically connects the plating stub 48A to acapacitor plate 372 formed in the GND layer and separated from otherelements in the GND layer by a gap 373. A portion of the SIG layeropposite the first capacitor plate 372 serves as a second capacitorplate 374, which is separated from the first capacitor plate 372 by adielectric material 375. Thus, the capacitor 50 schematically shown inFIG. 3 is embodied here as an embedded capacitor 350 that includes thefirst and second capacitor plates 372, 374 as separated by thedielectric material 375. The dielectric material 375 between thecapacitor plates 372, 374 is usually a material having a relatively highdielectric constant (K). The second capacitor plate 374 is a layerbetween SIG and GND, and is connected to GND as shown.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the invention. Asused herein, the singular forms “a”, “an” and “the” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise. It will be further understood that the terms “comprises”and/or “comprising,” when used in this specification, specify thepresence of stated features, integers, steps, operations, elements,components and/or groups, but do not preclude the presence or additionof one or more other features, integers, steps, operations, elements,components, and/or groups thereof. The terms “preferably,” “preferred,”“prefer,” “optionally,” “may,” and similar terms are used to indicatethat an item, condition or step being referred to is an optional (notrequired) feature of the invention.

The corresponding structures, materials, acts, and equivalents of allmeans or steps plus function elements in the claims below are intendedto include any structure, material, or act for performing the functionin combination with other claimed elements as specifically claimed. Thedescription of the present invention has been presented for purposes ofillustration and description, but it not intended to be exhaustive orlimited to the invention in the form disclosed. Many modifications andvariations will be apparent to those of ordinary skill in the artwithout departing from the scope and spirit of the invention. Theembodiment was chosen and described in order to best explain theprinciples of the invention and the practical application, and to enableothers of ordinary skill in the art to understand the invention forvarious embodiments with various modifications as are suited to theparticular use contemplated.

What is claimed is:
 1. A method, comprising: capacitively coupling aplating stub to ground so that the resonant frequency caused by theplating stub in a semiconductor package is shifted away from anoperational frequency.
 2. The method of claim 1, further comprising:forming the plating stub by electroplating a portion of a substratealong an electrical pathway extending from a periphery of the substrateto the portion of the substrate being electroplated.
 3. The method ofclaim 1, wherein capacitively coupling the plating stub to groundincludes connecting a first lead of a capacitor to the plating stub anda second lead of the capacitor to ground.
 4. The method of claim 1,wherein capacitively coupling the plating stub to ground includesforming an embedded capacitor in the substrate that couples the platingstub in an outer layer to a ground layer spaced from the outer layer. 5.The method of claim 1, wherein the semiconductor package includes aground layer and a first outer layer, wherein the first outer layerprovides a chip mounting location, a signal interconnect spaced from thechip mounting location, a signal trace extending from near the chipmounting location to the signal interconnect, and the plating stub,wherein the plating stub extends from the signal interconnect.